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Switch FET power handling
When FETs are used as series switch elements, you need to evaluate their power handling in the ON state. When they are configured as shunt elements, you need to calculate their power handling in the OFF-state.
When we say "power handling" for switches, what we mean is the power level that will correspond to the onset of gain compression. Once you exceed the calculated power handling, the insertion loss of your switch starts to go up. Typically you should try to operate a switch without compressing it, because you don't want to throw away performance on something as mundane as a switch, right?
The ultimate power at which a switch is damaged is the subject for another day...
Power handling for FETs in the ON state is calculated using the maximum current the device can pass:
The maximum current is proportional to the periphery of the device. Thus a 1 mm periphery device will have four times the power handling of a 0.5 mm device.
Using foundry parameters found on Northrop Grumman's foundry web site, a typical MESFET might have 225 mA/mm saturated current, and PHEMT might have 600 ma/mm IMAX. This means that a 1 mm Northrop Grumman PHEMT will handle 9 Watts at IDSS, while a 1 mm NG MESFET is good for 1.27 Watts.
The plot below shows the wide power handling variation that is possible for different FET peripheries with different normalized saturated current.
New for April 2008! This section has been expanded, please read on
The maximum power handling for FETs in the OFF state is mainly a function of breakdown voltage.
The greater the deference between pinch-off and breakdown, the higher the power handling. The optimum voltage for power handling is merely the arithmetic average of VBR and VPO:
Again referencing NG's foundry info, a GaAs MESFET could expect to have 2.2 volts pinch off and 19 volt breakdown, which translates to 2.8 watts power handling if you were to operate the switch with a control signal of exactly -8.4 volts, and all the planets were lined up (more on this in a minute). Northrop's typical GaAs PHEMT has 1.2 volt pinch-off and 10 volt breakdown will have maximum power handling of 0.77 watts, when operated at -8.4 volts.
Note that maximum OFF-state power handling is the same for all FETs that are of the same process parameters, regardless of FET periphery.
The above analysis assumes that you have biased your shunt FET power handling versus control voltage. Now let's look at how the power handling is affected by your choice of bias voltage. Let's define a parameter we'll call "overhead voltage". It is the minimum distance between the control voltage and either the pinch-off or the breakdown voltage (whichever is closer). If you operate at the optimum voltage, the overhead voltage we are defining is Vopt/2.
Note that the above equation assumes that VC is somewhere between VPO and VBR, but we didn't feel like adding the required "IF" statement to it here. The power handling can now be expressed as a function of the control voltage:
Let's look at a graph that shows how the control voltage affects the power handling. Below is a plot of power handling for a FET which has 12 volt breakdown and 2 volt pinch-off. At the optimum voltage of 7 volts it can handle 1 watt. But as you move away from the optimum, the power handling suffers a steep decline in both directions. A shift in either VBR, VPO or VC can reduce power handling quickly; if you use a high-value choke resistor for isolating the gate terminal, you'd better consider current leakage into the FET gate which will drift the operating point! Hence the planets have to align properly for maximum power handling to occur. Our advice is to always derate a switch by at least 20% (one dB) from it's maximum power handling.
If anyone wants the spreadsheet that does this analysis, just ask!
One advantage that PIN diodes have over GaAs FETs is in RF power handling. Vertical PIN diodes on GaAs can have breakdown voltages in excess of 30 volts, while PHEMT technology struggles to achieve breakdown voltages of 10 volts. The problem of power handling is worse than the 3:1 ratio of breakdown voltages, for power handling is proportional to voltage squared.
GaN technology has a huge advantage to GaAs PHEMT, because breakdown voltages of up to 100 volts are possible. Whether or not they become as ubiquitous as PIN diodes in switches will be determined by the small-signal loss they can achieve, which is a function of the switch figure of merit 1/(RONxCOFF).
"Stacking" FETs for higher power handling
Power handling in the OFF state can be increased by "stacking" FETs in series. If done properly the RF voltage will divide among the gates. Thus a double-stack of FETs with 12 volt breakdown can achieve comparable power handling to a PIN diode switch with 24 volts breakdown.
For stacked-FET switches, the power handling ideally goes up as the square of the number of FETs in the stack. A double-stack structure (two FETs in series) has four times the power handling of a FET structure, with one caveat: adequate isolation is needed between the adjacent gates so that the voltage divides equally. Resistive gate feeds are one way to accomplish this.
Another down side to stacking FETs to improve power handling in the OFF state is that the series resistance in the ON state is multiplied. You don't get anything for free!
One thing to consider is whether you need your switch to perform "cold" switching or "hot" switching. Hot switching means that it has a high-power signal incident on it during the switching cycle. Special considerations must be given to the switch design in this case or failure may occur.
More to come!
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