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New for December 2023. This is the third installment of an article on designing a four-bit phase shifter.
Click here to go to the first installment of a four-bit phase shifter design in MWO
Click here for the second installment of this article on phase shifter design, where we correct the RMS phase error calculation.
Click here to go to the fourth installment, where we design a MMIC 45-degree bit
Click here to go to the fifth installment, where we design a MMIC 90-degree bit
Click here to go to the sixth installment, where we design a MMIC SPDT switch used in a MMIC 180-degree bit
Click here to go to the seventh installment, where we design a MMIC 180-degree bit
Click here to go to the eighth installment, where we complete the four-bit MMIC phase shifter preliminary design
Before we look at the 22-degree bit design we need to discuss just a few subcircuits. Each one is modelled as microstrip on a 100um GaAs substrate, a popular choice for X-band control products.
Switch FET model
for this design we are using a very simple Switch FET model that includes some physical layout properties. It is located here. We could get a lot more elaborate with the model, but this one is simple and takes into account some significant parasitic properties of the device that are due to its physical size. The model uses switch FET figure of merit as in independent variable. Maybe someday we will get around to re-doing some of the design using two figures of merit so you can see that this parameter greatly affects insertion loss and usable bandwidth.
Another key characteristic of the switch FET model is that it includes two states (off and on) which are passed into the phase bit design so that it also includes two states.
Via hole model
You can see our simple microstrip via hole model here. In a final design, passive circuits will be analyzed in a 2.5D simulator such as Axiem.
22 bit model
This bit design uses a single series FET and two spiral inductors. How did we come up with the architecture? We started with the classic Campbell-Brown bit (reference below) Then we deleted the shunt FET just to see if it worked OK, like we discussed on this page. It seemed to work OK. We did not try to document any of the intermediate results, which took a couple of hours. That might make interesting toilet paper if you printed it all out, but the "final preliminary" design is what we will focus on. The shunt inductors are DC grounded through a via hole subcircuit. Note that every element in the circuit can generate a layout, except the switch FET, as it has two transmission lines that are not connected. The input and output series lines are both short sections of fifty-ohm microstrip.
One hierarchy above the bit design is a circuit we call "bit test", where the two states are analyzed in a four-port network. Port 1 to Port 2 is the phase state, and Port 3 to Port 4 is the reference state. The reference state convention we use is it is the state with the most-positive transmission phase (or the shortest delay).
Next we plotted the magnitudes of S11 and S21 for both states. There has been a ton of optimization to get to this point, we'll describe that later. Because the circuits are symmetric, there is no need to plot S22 as it will be the same as S11. But when the circuit model gets a little more detailed it will be a good idea to look at S22. The shaded lines are optimization goals.
The phase shift is also plotted (and optimized). In an equation block in the design file, we subtracted the unwrapped transmission phases of the two states to arrive at the phase shift. We'll show that within a future phase bit, this gets tricky when you get to 90 and 180 bits.
Now let's look at the optimization goals. We optimized teh phase to be 22.5 degrees from 9 to 11 GHz. How did we come up with the bandwidth? It seemed like it gave a nice response. Wider bandwidth=worse performance. Quit while youare ahead.
We optimized S11 (the phase state) toward -16 dB. Not shown is another optimization for S33 (the reference state) with the same goal.
We also optimized S21 (and S43) to try to hit -0.5 dB.
Here is a layout of the phase bit, after a few hours of tweaking. The FET is in the middle and consists of two transmission lines in series. In order to get the layout to snap together we had to go inside the FET and short it out, which is a PITA. One the next phase bit we will make the input and output networks into separate schematic blocks and create a layout-only circuit with a separate shorted FET, linking the FET dimensions from the global variables block. This little guy is done enough for now, let's move on to the 45-degree bit next month!
Reference
A Compact 5-bit Phase-Shifter MMIC for K-band Satellite Communication Systems
Campbell, C.F.; Brown, S.A.
IEEE Transactions on Microwave Theory and Techniques
Volume 48, Issue 12, December 2000