New for December 2023. This model was used in phase shifter design example that starts here.
Here is a switch model that will serve you well in "control circuit" MMIC designs, at least in the early stages. One important thing is that it includes the shunt capacitance of the FET structure, as well as inductance through the switch FET. A second important property is that it provides two states that are controlled by parameter "On".
Two main performance parameters of a switch FET are RON and COFF, which together determine the switch FET figure of merit, FC:
FC=2pi/(RON*COFF)
Learn more about that figure of merit here. The higher FC, the lower the loss and the wider bandwidth of your design. We chose to make FC and RON independent variables and compute COFF. RON is typically between 1 and 2 ohm-mm, where the millimeter dimension refers to gate periphery. COFF is typically around 0.3 pF/mm. Typical GaAs processes might have FC=200 GHz, which is bad news for designers hoping to show off their design skills. The actual on-resistance (RonQ) and off capacitance (CoffQ) of an instance of the model is calculated using "Q", the periphery of the device.
Here is a screen shot of our simple model.
Another important thing this model does is address the physical size of the FET, adding a pair of transmission lines to both ports. Parameters that affect the size are:
WF: width of drain fingers in microns (more accurately, the gate-to-gate spacing). Smaller is better, but foundries have design rules that govern this.
NF: number of gate fingers.
Q, the size of the transistor. It's periphery in mm. Read this Quora thread about why transistors are referred to as "Q", we prefer the explanation that has to do with the shape of early transistor packages. It is excellent lunch table trivia.
The overall size of the device is split so that half of it is located at port 1 and half of it is located at port 2. The size of a switch FET can be a limiting factor. Imagine if you made a single gate finger and it was a quarter-wave long!